-- Register File Entity
-- Chang Lan, <changlan9@gmail.com>
-- 11/9/2011

library IEEE;
use IEEE.std_logic_1164.all;
use work.global_definition.all;

entity regfile is
    port (
        clk, rst_n         : in  std_ulogic;
        write_enable       : in  std_ulogic;
        write_port         : in  std_ulogic_vector(width-1 downto 0);
        address_write_port : in  std_ulogic_vector(regfile_address_size-1 downto 0);
        address_port_0     : in  std_ulogic_vector(regfile_address_size-1 downto 0);
        address_port_1     : in  std_ulogic_vector(regfile_address_size-1 downto 0);
        read_port_0        : out std_ulogic_vector(width-1 downto 0);
        read_port_1        : out std_ulogic_vector(width-1 downto 0);
		read_port_ih       : out std_ulogic_vector(width-1 downto 0)
        );
end regfile;
